1. Field of the Invention
The invention is directed to a process for semiconductor devices and in particular to processes for making bipolar and metal-oxide-semiconductor (MOS) devices (BiCMOS devices) on a single silicon substrate.
2. Art Background
Integrated circuits in which bipolar transistors are combined with CMOS devices are currently desired for high performance systems such as multi-GHz communication large scale integrated circuits. As noted by Kinoshita, Y., et al., "Process Integration Technology for sub-30ps ECL BiCMOS using Heavily Boron Doped Epitaxial Contact (HYDEC)" IEDM, 94:17.4, pp. 441-444 (1994), integrating the processes for making the bipolar devices and the CMOS devices. Kinoshita et al. note that attempts to integrate the processes for fabricating the two types of devices on a single substrate have caused several problems. These problems include: 1) poor gate oxide reliability caused by subsequent masking and etching steps to for removing the gate oxide from the bipolar regions; 2) pMOS subthreshold voltage (V.sub.t) shift due to boron penetration during the thermal process sequence for bipolar graft base formation; and 3) enhancement of the short channel effect in pMOS caused by emitter drive-in thermal process.
To overcome these problems, Kinoshita et al. describe an integrated process for forming a bipolar device and an MOS device on a substrate. The integrate process utilizes a heavily doped epitaxial layer to both connect the base polysilicon electrode to the n-epi (collector) surface and as the diffusion source to form a bipolar graft base. The process described in Kinoshita is illustrated in the process flow sequence provided in FIG. 1. FIG. 1 illustrates the integrated steps for producing an MOS device and a bipolar device on a single substrate.
Referring to FIG. 1, in step 10 an n+ buried layer is formed in a silicon substrate. In step 20 a p+ buried layer is formed by high energy ion implantation followed by p-well and n-channel implantation. LOCOS (localized oxidation of silicon) isolation is performed in step 30, during which field oxide regions are formed on the silicon substrate. In step 40, the collector plug is formed by phosphorous ion implantation. N-well and p-channel implantations are performed in step 50, followed by the formation of a thin layer (7 nm thickness) of gate oxide, doped (boron for the bipolar device and either boron or arsenic or phosphorus for the MOS device) polysilicon (150 nm thickness) and silicon nitride layers (200 nm thickness) in step 60. The doped, polysilicon layer is the gate electrode of the MOS device and the base electrodes of the bipolar transistors.
In step 70 an emitter opening is formed and the gate oxide is removed from the bottom of the emitter opening using a wet etch. In this step a gap is formed under the undoped polysilicon layer. In step 80, heavily boron-doped epitaxial layer is then formed on the surface of the substrate using an ultra high vacuum chemical vapor deposition. In step 90, the heavily boron doped layer is selectively removed, leaving only that portion of the layer at the base of the emitter window. In step 100, a BF.sub.2 ion implantation is used to form the intrinsic base, followed by a phosphorous implantation for forming the selective ion-implanted collector (SIC) and oxide spacer formation. In step 110 the bipolar base electrode and MOS gate are formed simultaneously. In step 120, a furnace anneal was performed for bipolar emitter and extrinsic base drive-in. This annealing step also activates the source/drain and gate electrodes of the nMOS device.
One of the disadvantages of the above-described process is that the gap underlying the undoped silicon layer is difficult to fill when the size of the gap is less than 200 nm using chemical vapor deposition, because of the gaps that form in the fill as the fill material builds up on the bottom and top of the gap. Current CMOS technology requires gate oxide thicknesses of about 1.5 nm to about 6 nm. Since the gap results from the removal of the gate oxide, gap sizes are also in the range of about 1.5 nm to about 6 nm. As previously noted, gaps of this size are difficult to fill uniformly. Because a less than completely filled gap will cause problems in device performance, a process in which these gaps are completely filled in is desired.